A continuing trend in the field of semiconductor fabrication is to shrink device sizes and dimensions. So doing increases the density of devices on devices and leads to cost savings and performance enhancement. However, conventional fabrication processes can limit or prevent further scaling beyond certain limits.
Feature sizes relate to dimensions of individual components within a semiconductor device. In order to decrease or scale semiconductor devices, the feature sizes of the individual components are also reduced. If one or more of the feature sizes can not be reduced further, the semiconductor devices can be limited for further scaling. Critical dimensions include horizontal and vertical dimensions of features set by doping, layering, photolithography processes, and the like. Conventional fabrication processes result in minimum critical dimensions that can mitigate or prevent further scaling of semiconductor devices.
A significant critical dimension in semiconductor devices is the horizontal dimension of gate layers, post gate etch. This critical dimension can, if reduced, can permit further scaling of transistor semiconductor devices. Photolithography patterning processes employ patterning and resist materials to selectively remove portions of layers, such as gate layers, leaving selected portions as gates. However, conventional photolithography processes are limited to about 40 nanometers. At this dimension and below, photoresist begins to deform and break, also referred to as photoresist shrinkage. As a consequence, further scaling of transistor semiconductor devices including the gates can be limited and/or prevented.